The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation. The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
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The DOE will include an 8 run experiment with 2 center point runs for a total of 10 runs. This experimental setup is a half fractional factorial with resolution IV. Resolution IV means that main effects, each factor considered individually, are confounded with 3-way interactions. The PCB manufacturing processes selected as factors include laminate cooling rate, plating current density, pulse waveform, and hot air solder leveling (HASL) reflow. A confounded interaction cannot be separated out statistically from its 'aliased' main effect. This DOE is a screening design, which is preferred for early investigation since the likelihood that a 3-way interaction would dominate over a main effect is extremely unlikely.
For this DOE, some deviations from an ideal experimentation setup are present. Since each coupon has multiple holes, samples are not uniquely independent. Also, the factors of pulse waveform and current density are not independent.
The pulse waveform is also a nominal variable listed as a continuous factor for design purposes and has no center point value. The research identified PCB fabrication processes that were significant contributors to not only the incidence of cracks but also the length of cracks, in copper plated vias, after exposure to thermal shock excursions. Statistical analyses of the resultant DOE data identified the optimal settings for the four factors selected from the PCB fabrication processes. The binary logistic regression indicated that the likelihood of cracking increased from 220% to 561% across all via types when changing from water laminate cooling to air cooling within the same number of HASL reflow cycles. Since the plating is performed after the laminate cooling process, the influence of the laminate cooling process on the likelihood of cracking is not readily apparent.
Also, as the number of HASL reflows increased, the likelihood of crack occurrence increased from 25% to 77% across these via types, when holding the laminate cooling method constant. These results support the optimal recommendations of water cooling with HASL reflow of 1, as presented in Table 3. For 457.2 μm PTH, the only significant factor affecting crack length was the HASL reflow. For the 635 μm PTH, HASL reflow was also the most significant factor on the length of barrel cracks.
Other significant factors included current density and the second-order interaction effect between the laminate cooling method and current density. Figure 3 response slopes suggested a current density setting of 8 would reduce crack length and standard deviation, notably due to the interaction plot shown in Figure 14, where a setting of 14 coupled with standard water cooling should be avoided. For buried vias, laminate cooling method (air) was the most significant factor affecting the length of barrel cracks, even though the plating is performed after the laminate cooling process. Pulse waveform setting of 1 was the second most significant factor. Other significant factors included the second-order interaction effect between the laminate cooling method and current density, shown by Figure 17 and Figure 18, for the crack length average and standard deviation, respectively. This interaction effect further substantiated the optimal recommendations of standard cooling with current density 8, as presented in Table 3.
While the DOE was being conducted, the no-crack thermal shock requirement was reviewed for applicability against service life requirements. Multiple PCB coupon samples underwent close to 100 thermal shock cycles to determine when cracks initiated and to estimate crack growth rates. Engineering models estimated the service life correlating with 100 thermal cycles. This effort resulted in a relaxation of the crack criteria to allow up to 20% crack length of the specified minimum wall thickness. Submit A Comment Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted.
PWB Barrel Cracks – Wear Out Failures When exposed to thermal cycle testing, cracks that develop slowly in the copper barrel of plated through holes (PTH) is considered to be a wear out failure mode. This failure mode is often observed in boards that survive hundreds or thousands of thermal cycles and is the failure mode of robust PWBs.
Printed Circuit Board
This is a failure that develops slowly over time. There is an initiation of cracks in the barrel of the PTH that can advance through the metallization and the electrodeposited copper layers. The crack typically propagates along the boundary between copper crystals and traverses the thickness of the barrel in a tortuous path. Jude movie dvdrip 2017. The cracks usually initiate at glass fibers that are on the inner edge of the drill hole and frequently the crack angle is 30° to 50° off horizontal. Once initiated the cracks slowly develop over hundreds of cycles. With a wear out failure mode the damage accumulates at a constant rate. It is possible to create a graph of damage accumulation during thermal cycle testing by plotting resistance, taken at the maximum test temperature, for each cycle.
The initial resistance measurement of the first thermal excursion, at the maximum temperature, establishes the baseline condition against which subsequent measurements are compared. It is assumed that this first resistance measurement is a reflection of an undamaged circuit, and, if there is an increase in resistance in subsequent thermal cycles it is considered to reflect damage accumulation as a result of cracks in copper or separations between internal structures. A 10% increase in resistance, typically measured in milliohms, is considered a failure. The top of the graph is a failure at 10% increase in resistance; the x-axis variable is thermal cycles. Plotting a resistance graph of damage accumulation allows one to determine onset, rate of accumulation and if damage is accelerating.
Different failure modes tend to produce different damage profiles. Armed with a resistance graph, and cycles to failure data, insight on the failure mode can be gained. Degradation of copper and material and stress relief may be inferred by the damage profile.
A constant slow accumulation of resistance over the duration of the test suggests metal fatigue. Concerns and Considerations - Frequently cracks are in the central zone of the barrel of the PTH. During thermal excursions the PTH is under tension from z-axis expansion. Above the glass transition temperature (Tg), typically between 130°C and 190°C in “FR4” material, the coefficient of thermal expansion (CTE) in the z-axis is typically around 150 to 350 ppm/°C. The x-axis and y-axis compression of the copper barrel is approximately 20 to 40 ppm/°C above Tg. The warp and the weft of the glass fiber restrain thermal expansion in the x-axis and the y-axis.
The direction of the fiber glass warp exhibits a slightly lower CTE than the weft direction.